The present disclosure relates generally to the field of semiconductor devices and methods for fabrication, and more particularly to semiconductor via-fuses that have predictable fail locations. Semiconductor device fabrication is a multi-step process involving front-end-of-line (hereinafter “FEOL”) processing wherein the formation of individual devices, such as transistors, directly in a silicon wafer occurs and back end of line (hereinafter “BEOL”) processing wherein individual devices, for example, transistors, with wiring on the silicon wafer. BEOL generally begins when the first layer of metal wiring is deposited on the silicon wafer.
An electrical fuse (hereinafter “efuse”) is a common one time programmable device. Horizontal efuses are typically formed in the FEOL with a silicided gate polycrystalline silicon electrode material. Vertical efuses are typically formed in the BEOL using the same interconnection materials (lines and vias) as non-fuse areas. Efuses can be programmed to increase their resistance compared to unprogrammed efuses, which remain in a low resistance state. Programming is accomplished by controlling electromigration (hereinafter “EM”) of the fuse link from the anode to the cathode by one time complementary metal-oxide semiconductor activation. Ideally, a vertical e-fuse will blow in the via, however, current vertical efuse structures have unpredictable fail locations, which can affect the repeatability and reliability of BEOL via-fuse structures.